1. Field of the Invention
The present invention relates to a method of manufacturing an IC (Integrated Circuit) package, and more particularly to a method of manufacturing a stacked package having a PoP (Package on Package) structure.
2. Description of the Related Art
A semiconductor industry generally has an increasing trend of lightening, miniaturization, multifunction, and high performance in addition to cheap production. One critical technique required to meet such a trend is IC packaging.
IC packaging involves protecting semiconductor chips such as a single device and an IC formed by stacking a variety of electronic circuits and wirings from various external environments such as dust, moisture, and electric and mechanical loads, forming the semiconductor chips with signal input/output terminals to/from a main board using a lead frame, a PCB (Printed Circuit Board), or the like to optimize and maximize electric performance of the semiconductor chips, and molding the semiconductor chips using an encapsulant.
Meanwhile, as products to which an IC package is mounted recently have a light, thin, short, and small structure and require many functions, a method such as a SIP (System in Package) method or a PoP (Package on Package) method by which a plurality of semiconductor chips is mounted in the IC package is applied as the IC packaging technique.
Moreover, a PCB on which high-integrated and ultrathin components are mounted should also be thin. This enables increased freedom in circuit design of the board, and thus various techniques such as a micro via process and a build-up process are adopted to solve the issue.
In particular, a micro via-hole is receiving attention as a method for satisfying high integration and fine wiring pitch demand as a degree of integration of a semiconductor device is currently increased.
In particular, an MLB (multi layer board) is configured only by a through-hole passing through all layers. However, a blind via-hole through which interlayer conduction may be selectively performed is in the limelight since a build-up PCB further requires high-density wirings.
A mechanical drilling process, a plasma etching process, a laser drilling process, or the like is generally known as a method of forming the blind via-hole of the PCB.
In particular, the laser process is currently the most widely used method to form the blind via-hole of the PCB and includes processes using excimer, Nd:YAG, and CO2 laser drills.
FIGS. 1A to 1C are views illustrating a process of forming via-holes by a conventional laser drilling process. First, a semiconductor chip 20 is stacked on a PCB 10 and then a molding portion 30 is formed, as shown in FIG. 1A. Next, laser drilling positions 40 are determined on parts of the molding portion 30 to be formed with via-holes by the coordinate and then the parts are drilled using a laser, as shown in FIG. 1B. Consequently, TMVs (Through Mold Vias) 50 are formed as shown in FIG. 1C.
However, the laser drilling process has a limit to realize a fine pitch equal to or less than 0.3 mm. Since a laser drilling position is determined on an upper surface of a mold with no mark by the coordinate after an EMC molding process in the laser drilling process, a via-hole may be formed at an inaccurate position, thereby causing an error.
Moreover, process equipment such as a plasma cleaner, a reflow M/C, a flux cleaner, and an off-loader may be additionally required in order to remove residues generated during the laser drilling process. Since the laser equipment is expensive, equipment investment may be costly.
[Patent Document 0001] Korean Patent Publication No. 10-0674316 (Jan. 18, 2007)